AMD's Next-Generation Zen 6 CPU Family
According to information shared with engineers at top motherboard vendors, AMD's upcoming Zen 6 CPU family will utilize a combination of TSMC's N3 and N2 process nodes. The plans include five different silicon lines that are scheduled to launch in late 2026 for servers, desktops, and notebooks.
On the server side, the EPYC "Venice" lineup will be divided into two categories: Venice classic for general-purpose use and Venice dense for high-density cloud applications. Both versions will utilize TSMC's custom-tuned N2P process, providing an 8-10% increase in clock speed compared to the current N3E. The classic die will now have 12 Zen 6 cores, while the dense die will house 32 Zen 6 cores, allowing for up to 256-core, 512-threaded dense packages when eight dies are interconnected through the existing organic interposer.
For client systems, AMD has chosen codenames that indicate their intended purposes. "Olympic Ridge" will power the Ryzen 10000 desktop series on the N2P node, while "Gator Range" is aimed at gaming laptops with power exceeding 55 W. The mainstream thin-and-light segment will be catered to by "Medusa Point," which features a hybrid design combining an N2P compute tile with an N3P I/O tile. Entry-level models may opt for a more cost-efficient monolithic N3P die. Additionally, there are plans for a more detailed "Medusa Halo" series and a budget-friendly "Bumblebee" series, although their process allocations are still being reviewed.
AMD and TSMC have closely collaborated on optimizing metal layers and libraries, resulting in the final silicon closely resembling an "N2-AMD" stack rather than a standard N2P node. The first silicon samples are expected back from the fab before Christmas, with volume production scheduled to coincide with the 2026 back-to-school notebook cycle and a subsequent server refresh wave.
